1. Technical Field
The present invention relates to a semiconductor integrated circuit, a checking device and a method of checking the semiconductor integrated circuit, and particularly, is suitable for an application to a method of checking an ASIC (Application Specific Integrated Circuit).
2. Related Art
In a method of checking a semiconductor integrated circuit according to the related art, an IC chip attached onto a circuit board is tested by using a JTAG (Joint Test Action Group) test port. The JTAG standard is defined by an IEEE 1149.1, “IEEE Standard Test Access Port and Boundary—Scan Architecture”. The JTAG test port has the function of outputting information about an internal register or an input/output bus.
For example, Japanese Patent Application Publication 2003-57300 discloses a method of incorporating a checking circuit into an integrated circuit and receiving, through a receiving section, an electromagnetic wave discharged from the feeding and transmitting/receiving antenna of a checking device, thereby generating the driving power of the checking circuit in order to carry out a check without supplying the driving power to a circuit or a board. Moreover, it is also possible to receive a check control procedure from the checking device in a non-contact mode in the same manner and to cause a control logic to control an analog SW, a D/A circuit and an A/D circuit in accordance with the received control procedure to check a circuit through a checking wiring, thereby transmitting the result of the check to the checking device through an encoder and a transmitting section.
In the JTAG test port, however, information is exchanged through a serial communication of approximately 10 Mbps. For this reason, the JTAG standard has a problem in that it is impossible to handle a sufficient information amount for monitoring information about a register or a bus connected to a CPU subjected to multibit processing.
Moreover, there is a problem in that a package size is increased when a pin for outputting the signal of an internal bus in an ASIC to the outside of an IC package is provided in order to monitor the signal of the internal bus in the ASIC. Furthermore, there is also a problem in that a noise might be added to the signal of the internal bus, thereby causing a malfunction.
In addition, the method disclosed in Japanese Patent Application Publication 2003-57300 serves to receive a checking procedure from the outside to check the state of a circuit and to transmit the result of the check to the outside, and has a problem in that the check cannot be carried out in a procedure other than a predetermined procedure.